Fixed incorrect memory clock reported for AMD 19h 60-6fh chipsets.Fixed incorrect memory clock reported for Intel Alder Lake/Rocket Lake chipsets.Fixed channel decoding for AMD Ryzen Zen 2/4 chipsets.
Fixed hang due to reading non-existent MSR registers for AMD 19h 60-6fh chipsets.Added support for chipsets with up to 12 memory controllers.Added DIMM/IC decoding support for AMD Phoenix (19h 74h) chipsets.Implemented workaround for reading DDR5 SPD when SPD write disable (SPDWR) is set for Intel chipsets.Added 'SPDREPORTBYELO' and 'SPDREPORTBYTEHI' configuration parameter for specifying the SPD byte range to display in the HTML report.